1. Field of the Invention
The present invention relates to a semiconductor memory device such as a MOS memory, and more particularly, it relates to a static RAM having a load circuit capable of setting bit lines to an intermediate voltage.
2. Related Background Art
FIG. 1 is a circuit diagram around the bit lines of a conventional static random access memory (SRAM). As shown in FIG. 1, disposed between two bit lines BLA and BLB are a plurality of memory cells MC1, MC2 to MCn, an initialization circuit 1 for initializing the voltages of these bit lines BLA and BLB, and a load circuit 2 capable of setting the bit lines BLA and BLB to an intermediate voltage so that low level voltage of the bit lines BLA and BLB does not lower excessively. Each of these circuits is constituted of MOS transistors.
The initialization circuit 1 includes an equalizing transistor Q1 for short-circuiting both the bit lines BLA and BLB during the address transition of memory cells, that is, when carrying out change-over between selection and non-selection of the memory cells, and precharge transistors Q2 and Q3 for precharging the bit lines BLA and BLB, respectively. The gate terminals of these transistors Ql to Q3 are all connected to a signal FI1. The voltage level of the signal FI1 is controlled by an address transition detecting circuit (not shown), set to a high level in a stationary state, and temporarily set to a low level during the address transition. That is, the signal to be supplied to the signal FI1 is a one shot pulse signal, and the address transition detecting circuit is constituted of a known one shot pulse generating circuit.
The load circuit 2 has load transistors Q4 and Q5 for setting the low level voltages of the bit lines BLA and BLB to the intermediate voltage, respectively. The gate terminals of these transistors Q4 and Q5 are all connected to a ground terminal, and they are always in an ON state.
The memory cells MC1,MC2-MCn are constituted of, for example, a known circuit as shown in FIG. 2. FIG. 2 shows an example in which the memory cells MC1, MC2 . . . are constituted of two PMOS transistors Q11 and Q12 and four NMOS transistors Q13 to Q16. The NMOS transistors Q13 and Q14 turn on/off in accordance with logic of a word line WL. The transistors Q11 and Q15 are connected in series between a power supply terminal VDD and an ground terminal VSS, and the transistors Q12 and Q16 are connected in series between the power supply terminal VDD and the ground terminal VSS. The gate terminals of the transistors Q1 and Q15 are connected to the drain terminal of the transistor Q14, and the gate terminals of the transistors Q12 and Q16 are connected to the drain terminal of the transistor Q13.
The memory cells MC1 and MC2 of FIG. 1 are both connected to the bit lines BLA and BLB, the memory cell MC1 is connected to a word line WL1, and the memory cell MC2 is connected to a word line WL2.
FIG. 3A is a diagram showing the voltage changes of the bit lines BLA and BLB during the address transition, FIG. 3B is a diagram showing the voltage change of the signal FI1 during the address transition, and FIG. 3C is a diagram showing the voltage changes of the word lines WL1 and WL2 during the address transition. FIG. 3 shows the voltage change in the case of transiting from the status selecting the memory cell MC1 to the status selecting the memory cell MC2 when data "1" is recorded to the memory cell MC2.
Before the address transits, the word line WL1 is an active status, (e.g., high level), and the word line WL2 is an inactive status, (e.g., low level). Because of this, MC1 is selected, the bit line BLA becomes low level, and the bit line BLB becomes high level. In this case, the voltage level of the bit line BLA becomes the intermediate voltage between the power supply voltage VDD and the ground voltage VSS. The reason why the bit line becomes the intermediate voltage is that the load transistors Q4 and Q5 are always in ON state, and the electric charge from the power supply terminal VDD is supplied to the bit line BLA via the load transistors Q4 and Q5.
As described above, by setting the low level voltages of the bit lines BLA and BLB to the intermediate voltage, the voltages of the bit lines BLA and BLB can quickly be raised to an initialized voltage during the address transition as described later. Additionally, the initialized voltage is the same voltage as the power voltage VDD.
On the other hand, when the address transits, the word line WL1 becomes an inactive state, whereby the memory cell MC1 becomes a non-selected state. Moreover, since the signal FI1 reaches the low level during the address transition period, the equalizing transistor Q1 is in ON state, and both of the bit lines try to reach the same voltage. At the same time, the precharge transistors Q2 and Q3 become ON state, and as a result, the bit lines BLA and BLB are charged to reach the same voltage level as the initialized voltage VDD via the precharge transistors Q2 and Q3.
As described above, in the circuit of FIG. 1, by using the equalizing transistor Q1 and precharge transistors Q2 and Q3, while equalizing the bit lines BLA and BLB, and precharging to reach the level of the voltage VDD when the address transits, the bit line voltages are initialized.
Moreover, when the initialization processing of the bit lines BLA and BLB is started (time T1 of FIG. 3), the low level voltages of the bit lines BLA and BLB are set to the intermediate voltage between the power voltage VDD and the ground voltage VSS, and the voltages of the bit lines BLA and BLB can quickly be raised to the initialized voltage VDD.
Subsequently, the signal FI1 showing in FIG. 1 returns to the high level, the equalizing transistor Q1 and precharge transistors Q2 and Q3 are placed in OFF state, and the initialization processing of the bit line voltages is finished. At the same time, the word line WL2 becomes the active state by the address transition, and the memory cell MC2 is selected. When data "1" is stored in the memory cell MC2, the voltage of the bit line BLB reaches the low level, and the voltage of the bit line BLA reaches the high level.
In this case, since the load transistors Q4 and Q5 are in ON state, the voltage of the bit line BLB reaches the intermediate level between the power voltage VDD and the ground voltage VSS.
However, the circuit of FIG. 1 has a problem that the low level voltages of the bit lines BLA and BLB does not quickly lower until the desired voltages after the initialization processing of the bit lines BLA and BLB is finished.
More specifically, in the circuit of FIG. 1, at the same time when the initialization processing of the bit lines BLA and BLB is finished, the word line WL2 becomes the active state. Therefore, the data of the memory cell MC2 is outputted to the bit line BLB, and the bit line BLB reaches the low level. However, since the load transistors Q4 and Q5 are always in ON state, the bit line BIB is always supplied with the electric charge via the load transistors Q4 and Q5. Therefore, the voltage amplitude of the bit line BLB does not increase soon, and an access time delay occurs.